The present invention relates generally to a semiconductor memory device and its operation method and more specifically to redundant memory cells used to replace defective memory cells in a semiconductor memory device and its operation method.
It is a continuing goal to improve the overall yield of good semiconductor memory devices in order to reduce manufacturing costs. As the degree of integration of a semiconductor memory device becomes greater, the likelihood of occurrence of defective memory cells increases. One method of improving yield is through the use of redundant memory cells that can be used to replace defective memory cells. By replacing defective memory cells with redundant memory cells, some devices that include defects can be saved, thus yield can be improved and manufacturing costs may be reduced.
It is desirable, that when defective memory cells are replaced with redundant memory cells, that the redundant memory cells are properly characterized for the possibility of defects. This can reduce the likelihood of defective parts from being included in parts shipped to customers.
One method of testing is a cell stress test. In a cell stress test, all memory cells have a potential written into them so that a high electric field can be induced across a dielectric layer in each memory cell. However, in some cases it may be required to know the physical layout of the memory cells to determine whether a logic zero or a logic one needs to be written into a particular address location in order to ensure that the proper potential is written into the particular memory cell corresponding to the particular address location. However, when a redundant memory cell is used to replace a defective memory cell, the particular physical cell layout mapping with respect to address values is modified. This can have adverse affects on such a cell stress test and therefore compromise test results.
One such method of addressing this problem has been disclosed in Japanese Laid-Open Patent Publication No. Hei 11-203889 and will be discussed with reference to FIG. 1.
Referring now to FIG. 1, a block schematic diagram of a conventional semiconductor memory device is set forth and given the general reference character 100.
Conventional semiconductor memory device 100 has an address buffer 117, a row decoder 113, a column decoder 115, a spare row decoder 114, a memory cell array 101, a sense amplifier circuit 103, a program circuit 119, a block decision section 116, a data scramble control circuit 120, a clock generator circuit 121, a logical gate 122, an input buffer 111, a scramble circuit 108, and an output buffer 105. The output buffer 105 has a preamplifier 107, scramble circuit 108, and a main amplifier 109.
Memory cell array 101 has normal memory cells and redundant memory cells. When a normal memory cell is defective, it is replaced by a redundant memory cell. Each normal memory cell and each redundant memory cell stores either true data or complementary data. True data means that the stored data in a memory cell has a high potential when a data one is stored and a low potential when data zero is stored. Complementary data means that the stored data in a memory cell has a low potential when a data one is stored and a high potential when data zero is stored.
Block decision section 116 determines whether or not a redundant memory cell that replaces a normal memory cell stores data that is inverted with respect to data that would be stored in the replaced normal memory cell.
Data scramble control circuit 120 generates a scramble on signal SON having a high logic level when a redundant memory cell is stored data that is inverted with respect to data that would be stored in the replaced normal memory cell. When scramble on signal SON has a high logic level, scramble circuit 110 reverses write data to be written in the redundant memory cell. Likewise, to keep data coherency, when scramble on signal SON is high, scramble circuit 108 reverses read data read from the redundant memory cell.
In this way, conventional semiconductor memory device 100 writes data at the same potential level in a redundant memory cell as would be written in the replaced memory cell if it were not defective. Thus, it is possible to perform a stress test in which stress can be applied to the redundant memory cell in a similar manner as the normal memory cell.
However, in stress tests, it is also important to consider cell to cell breakdown conditions. In this case, it is important to write patterns so that the potential written into adjacent or nearby memory cells are known. In this way, a cell to cell stress can be performed.
Consider a test in which data one is written to all memory cells. When data one is written to all cells, half of the memory cells receive a high potential and half of the memory cells receive a low potential. Thus, cell to cell stress can be tested.
In this example, a first redundant memory cell stores a logic one with a high potential, a second redundant memory cell (physically adjacent to the first redundant memory cell) stores a logic one with a low potential, and a normal memory cell stores a logic one with a high potential. When the first redundant memory cell is used and the second redundant memory cell is not used, a high potential is written in the first redundant memory cell and a low potential is written into the second redundant memory cell. Thus, stress between the first and second redundant memory cells is tested. However, when the normal memory cell is replaced by the second redundant memory cell, inverted write data is written into the second redundant memory cell. Thus, a high potential is written into both the first and second redundant memory cells. In this case, cell to cell stress between the first and second redundant memory cells is not properly tested and defects may not be captured in testing.
It is desirable to keep similar electrical stress conditions in a redundant memory cell that is used to replace a normal memory cell as would occur in the normal memory cell.
In light of the above discussion, it would be desirable to provide a semiconductor memory device where electrical stress conditions in a redundant memory cell that is used to replace a normal memory cell may be similar to electrical stress conditions as would occur in the normal memory cell.
A semiconductor memory device according to the present embodiments may include a plurality of normal memory cells and redundant memory cells. Normal memory cells may include true normal memory cells and complement normal memory cells. Redundant memory cells may include true redundant memory cells and complement redundant memory cells. When a normal memory cell is found to be a defective memory cell, it may be replaced by a replacement redundant memory cell from the plurality of redundant memory cells. A defective memory cell that is a true normal memory cell may be replaced with a replacement memory cell that is a true redundant memory cell and a defective memory cell that is a complement memory cell may be replaced with a replacement memory cell that is a complement redundant memory cell. In this way, electric and physical conditions of a replacement memory cell may be essentially the same as the electric and physical conditions of the defective memory cell would have been had it not been replaced.
According to one aspect of the embodiments, a memory device may include a plurality of normal memory cells and plurality of redundant memory cells. Normal memory cells may include a first memory cell type that may store a first logic level with a first memory cell state and a second memory cell type that may store the first logic level with a second memory cell state. Redundant memory cells may include a first redundant memory cell type that may store the first logic level with the first memory cell state and a second redundant memory cell type that may store the first logic level with the second memory cell state. A replacement section may replace at least one normal memory cell with at least one redundant memory cell when the at least one normal memory cell has been determined to be defective. The replacement section may replace the at least one normal memory cell with the at least one redundant memory cell in accordance with whether the at least one normal memory cell is of the first memory cell type or the second memory cell type.
According to another aspect of the embodiments, the replacement section may replace the at least one normal memory cell with the at least one redundant memory cell so that the at least one normal memory cell of the first memory cell type is replaced with the at least one redundant memory cell of the first redundant memory cell type.
According to another aspect of the embodiments, the replacement section may replace the at least one normal memory cell with the at least one redundant memory cell so that the at least one normal memory cell of the second memory cell type is replaced with the at least one redundant memory cell of the second redundant memory cell type.
According to another aspect of the embodiments, the replacement section may be coupled to receive a test instruction signal. When the test instruction signal has a first test logic level, the replacement section may replace the at least one normal memory cell with the at least one redundant memory cell in accordance with whether the at least one normal memory cell is of the first memory cell type or the second memory cell type. When the test instruction signal has a second test logic level, the replacement section may replace the at least one normal memory cell with the at least one redundant memory cell independently from whether the at least one normal memory cell is of the first memory cell type or the second memory cell type.
According to another aspect of the embodiments, each of the plurality of normal memory cells and the plurality of redundant memory cells may include a memory cell capacitor for storing a data value in accordance with a storage potential. The first memory cell state may be a state where the first logic level is stored with the storage potential higher than a predetermined potential and the second memory cell state may be where the first logic level is stored with a storage potential lower than the predetermined potential.
According to another aspect of the embodiments, the replacement section may include an address scramble circuit coupled to receive an address and generate a redundant address in accordance with whether the at least one normal memory cell is of the first memory cell type or the second memory cell type.
According to another aspect of the embodiments, an operation method for a memory device including a plurality of normal memory cells and a plurality of redundant memory cells may include the step of defining at least one replacement redundant memory cell from the plurality of redundant memory cells, when at least one of the normal memory cells has been determined to be a defective normal memory cell, to replace the at least one defective normal memory cell. The plurality of normal memory cells may include a first memory cell type that may store a first logic level with a first memory cell state and a second memory cell type that may store the first logic level with a second memory cell state and the plurality of redundant memory cells may include a first redundant memory cell type that may store the first logic level with the first memory cell state and a second redundant memory cell type that may store the first logic level with the second memory cell state. The method may further include the step of providing an address such that if the address corresponds to the at least one of the normal memory cells that has been determined to be defective, the at least one replacement redundant memory cell from the plurality of memory cells is selected such that if the at least one of the normal memory cells that has been determined to be defective is of the first memory cell type, the at least one replacement redundant memory cell is of the first redundant memory cell type.
According to another aspect of the embodiments, if the at least one of the normal memory cells that has been determined to be defective is of the second memory cell type, the at least one replacement redundant memory cell may be of the second redundant memory cell type.
According to another aspect of the embodiments, a memory device may include a plurality of normal memory cells and a plurality of redundant memory cells. Normal memory cells may include a first memory cell type that may store a first logic level with a first memory cell state and a second memory cell type that may store the first logic level with a second memory cell state. Redundant memory cells may include a first redundant memory cell type that may store the first logic level with the first memory cell state and a second redundant memory cell type that may store the first logic level with the second memory cell state. A replacement section may replace at least one normal memory cell with at least one redundant memory cell when the at least one normal memory cell has been determined to be defective. In a first operating mode, the replacement section may replace the at least one normal memory cell with the at least one redundant memory cell so that normal memory cells of the first memory cell type are replaced with redundant memory cells of the first redundant memory cell type and normal memory cells of the second memory cell type are replaced with redundant memory cells of the second redundant memory cell type.
According to another aspect of the embodiments, the first operating mode may be a test mode.
According to another aspect of the embodiments, in a second operating mode, the replacement section may replace the at least one normal memory cell with the at least one redundant memory cell so that normal memory cells are replaced independently from whether the at least one normal memory cell is of the first memory cell type or the second memory cell type.
According to another aspect of the embodiments, the replacement section may be coupled to receive a plurality of addresses and provide a plurality of redundant select signals.
According to another aspect of the embodiments, the replacement section may include a redundant address decision circuit coupled to receive at least a first portion of the plurality of addresses and may provide a replacement instruction signal. An address scramble circuit may be coupled to receive at least a second portion of the plurality of addresses and the replacement instruction signal and may provide at least one redundant address.
According to another aspect of the embodiments, the address scramble circuit may include a scramble control circuit and an address mapping circuit. The control circuit may be coupled to receive at least a first one of the second portion of the plurality of addresses and the replacement instruction signal and may provide an address mapping control signal. The address mapping circuit may be coupled to receive the address mapping control signal which determines the mapping of the at least one redundant address with respect to at least a second one of the second portion of the plurality of addresses.
According to another aspect of the embodiments, the address mapping control circuit may be coupled to receive a first operating mode signal that has a first operating mode logic level when the memory device is in the first operating mode.
According to another aspect of the embodiments, the address mapping circuit may include a plurality of transfer gates coupled to receive the address mapping control signal and may provide a controllable impedance path between the at least the second one of the second portion of the plurality of addresses and the at least one redundant address.
According to another aspect of the embodiments, a plurality of word lines may be disposed in a row direction and a plurality of bit lines may be disposed in a column direction. The at least one replacement memory cell may be included in a first redundant row of redundant memory cells and the at least one defective normal memory cell may be included in a first normal row of normal memory cells.
According to another aspect of the embodiments, when the at least one replacement memory cell replaces the at least one defective normal memory cell, the first redundant row of redundant memory cells may replace the first normal row of normal memory cells and a second redundant row of redundant memory cells adjacent to the first redundant row of redundant memory cells may replace a second normal row of normal memory cells adjacent to the first normal row of normal memory cells.
According to another aspect of the embodiments, a plurality of word lines may be disposed in a row direction and a plurality of bit lines disposed in a column direction. The at least one replacement memory cell may be included in a first redundant column of redundant memory cells and the at least one defective normal memory cell may be included in a first normal column of normal memory cells
According to another aspect of the embodiments, when the at least one replacement memory cell replaces the at least one defective normal memory cell, the first redundant column of redundant memory cells may replace the first normal column of normal memory cells and a second redundant column of redundant memory cells adjacent to the first redundant column of redundant memory cells may replace a second normal column of normal memory cells adjacent to the first normal column of normal memory cells.